Direct slave addressing to indirect slave addressing

ABSTRACT

A computer bus system comprises: a direct address bus; at least one bus master device and at least one bus slave device, the bus master device and bus slave device being connected to the bus so that the bus master device may communicate with the bus slave device over the bus. The bus has an address space assigned to different devices connected to the bus and is a multiplexed address/data bus for transferring blocks of data ( 63,76 ) in a direct address transaction ( 60 ) between the devices. Each direct address transaction ( 60 ) comprises a burst transaction ( 61 ) having an address phase ( 12,62 ) with a bus space address value ( 62 ) followed by a data phase ( 63 ). The bus slave device includes an indirect address device addressable in an indirect address transaction ( 70 ) that has an address register load transaction ( 71 ) followed by a data register load transaction ( 72 ). The indirect address device has a memory with memory locations identified by address values loaded into the address register of the indirect address device. The slave device includes a transaction translation device between the bus and the indirect address device that translates the direct address transaction ( 61 ) to an indirect address transaction ( 70 ) including mapping ( 64 ) the bus space address value ( 62 ) to the destination address value ( 74 ). Therefore, a direct address transaction ( 60 ) received by the slave device for communicated blocks of data is presented to the indirect address device as an indirect address transaction ( 70 ).

TECHNICAL FIELD

[0001] The present invention relates to a computer bus system which usesdirect addressing, where devices may be accessed using either directaddressing or indirect addressing.

BACKGROUND OF THE INVENTION

[0002] Computer busses such as the PCI bus and J-Bus, multiplex theaddress and data onto a common bus. The address is presented for oneclock cycle followed by the data on the next clock cycle. This has theadvantage of halving the number of connections needed when compared witha non-multiplexed bus. For example, the PCI bus is a 32-bit bus with 32data lines for communicating 32-bit words between devices connected tothe bus. If the PCI bus did not multiplex address and data, there wouldneed to be 32 lines for both data and address, making a total of 64lines. Such a non-multiplexed bus would be relatively costly toimplement, and would require a more complex system board.

[0003] To achieve fast data transfer on a multiplexed bus, ‘burst’transfers are used. This involves a single address word ‘A’ followed byone or more data words where the first data word ‘D0’ is the data foraddress ‘A’, the second data word ‘D1’ is the data for address ‘A+1’,‘D2’ is the data for address ‘A+2’, and so on. Each transactiontherefore consists of an address phase followed by a data phase. Such aprotocol for transferring data is known as “direct addressing”, anddevices that use this are called “direct address” devices. Directaddress devices automatically increment the address for each sequentialdata word during the transfer of a block of data.

[0004] If a direct address burst is terminated before the data transferis complete, when the burst resumes there must be a new address cyclegiving the address of the next data word as shown below.

[0005] Certain devices which may be connected to a bus usingaddress/data multiplexing, use a different protocol for communicatingdata to or from the bus. These devices are known as “indirect addressdevices” and use a protocol called “indirect addressing”, in which anaddress value is loaded in a first transaction into an “addressregister” of the device. The data is then loaded in a second transactioninto a data register which may be a burst transaction of data into thedata register. Indirect address devices automatically increment theaddress for each sequential data word during the transfer of a block adata. Thus this whole process involves two separate transactions acrossthe bus to the memory of the indirect address device.

[0006] An advantage of indirect addressing is that it permits a muchlarger address space to be accessed within an indirect address device,whilst occupying a much smaller area of address space on the bus.

[0007] It is possible to access an indirect address device across adirect address bus by communicating sequentially two direct addresstransactions. During the address phase of the first transaction, theaddress of the address register is presented onto the bus, then duringthe data phase the address value is loaded into the address register. Inthe second transaction, the address of the data register is presentedonto the bus during the address phase, followed one or more sequentialdata words loaded into the data register during the data phase loads.

[0008] Although it is possible to use an indirect address device on adirect address bus, there are two main problems that make it difficultin practice to integrate an indirect address device with a directaddress bus. The first of these is that if there are other devicesconnected to the bus which may communicate with the indirect addressdevice, then these other devices may attempt to access the indirectaddress device in between the two sequential direct address transactionsneeded to complete the indirect address transaction. The second problemis that some direct address devices do not have the capability toperform two sequential direct address transactions to communicate withan indirect address device. Although it is in principle possible todevise a bus control system to avoid such problems, existing hardwareand software for many applications will have to be completely redesignedto ensure that direct address devices can reliably communicate withindirect address devices using two sequential direct addresstransactions.

SUMMARY OF THE INVENTION

[0009] It is an object of the present invention to provide a computerbus system that addresses these problems.

[0010] Accordingly, the invention provides a computer bus system,comprising: a bus; at least one bus master device and at least one busslave device, the bus master device and bus slave device being connectedto the bus so that the bus master device may communicate with the busslave device over the bus; wherein:

[0011] i) the bus has an address space with parts of the bus addressspace being assigned to different devices connected to the bus;

[0012] ii) the bus is a multiplexed address/data bus for transferring ina direct address transaction between said devices, blocks of data, eachof said direct address transactions comprising one or more bursttransactions consisting of an address phase followed by a data phase,the address phase including a bus space address value;

[0013] iii) the bus slave device includes an indirect address device,addressable in an indirect address transaction, said transactioncomprising an address register load transaction followed by a dataregister load transaction;

[0014] iv) the indirect address device has a memory with memorylocations identified by address values;

[0015] v) the address register load transaction comprises a destinationaddress value for blocks of data communicated to/from the memory of theindirect address device;

[0016] wherein the slave device includes a transaction translationdevice between the bus and the indirect address device, the transactiontranslation device being adapted to translate a direct addresstransaction on the bus to an indirect address transaction including amapping of the bus space address value to the destination address value.

[0017] The bus may be a system bus, for example for a personal computer.Alternatively, the bus may be a local bus, such as a J-bus, for examplea dedicated bus connecting a number of devices together separate fromany other general bus such as one linking the devices to a systemmicroprocessor.

[0018] Therefore, a direct address transaction received by the slavedevice is presented to the indirect address device as an indirectaddress transaction. In other words, one direct address transaction canbe translated to construct two sequential transactions to access theindirect address device.

[0019] The data transferred in the indirect address transaction may bedata that is either written to the slave device from the master device,or data that is read from the slave device to the master device.

[0020] In a preferred embodiment of the invention, the address valuesfor the indirect address device are used to identify both an addressregister and a data register in the indirect address device. The addressregister load transaction for blocks of data communicated to/from thememory of the indirect address device may then comprise two addressvalues: an address register value and the destination address value. Thedata register load transaction then includes a data register addressvalue. The transaction translation device, as part of the translation ofthe direct address transaction to the indirect address transaction, canthen be arranged to generate both the address register address value andthe data register address value.

[0021] In particular, the transaction translation device may translatethe direct address transaction to the indirect address device asfollows. First, the transaction translation device generates the addressregister address value for the indirect address device. It thentranslates the address value from the bus and loads it into the addressregister of the indirect address device. Then, it generates the dataregister address value for the indirect address device. Finally, iteither passes the data word or words transparently through from the busand loads them into the data register of the indirect address device, ifit is a data write transaction, or it passes the data word or wordstransparently through from the indirect address device data register tothe bus, if it is a data read transaction.

[0022] The invention is therefore applicable to the case of a computerbus system conforming to the direct address protocol of busses such asthe PCI bus, as used in personal computers, or the J-Bus as used by theIntel i960 family of microprocessors, and bus slave devices such asthose based on the Expansion Bus (Xbus) standard, as implemented in theTMS320C6 series of digital signal processing (DSP) chips manufactured byTexas Instruments, Inc.

[0023] A block of data may comprise one or more data words, for example32-bit data words. The data register load transaction may then comprisethe data register address value followed by one or more data words.

[0024] The address of the address register and the address of the dataregister could be communicated by the master device to the slave device,therefore, either or both of the address register address value and/orthe data register address value may be alterable and stored in thetransaction translation device.

[0025] This, however, is information that does not normally need to bealtered, therefore in some cases it is preferred if the address registeraddress value and the data register address value are both fixed andgenerated internally by the transaction translation device.

[0026] Also according to the invention, there is provided a method ofcommunicating blocks of data over a computer bus system, the systemcomprising: a bus, the bus having an address space and being amultiplexed address/data bus for transferring in a direct addresstransaction blocks of data; at least one bus master device and at leastone bus slave device, the bus master device and bus slave device beingconnected to the bus so that the bus master device may communicate withthe bus slave device over the bus, the bus slave device including anindirect address device; the indirect address device has a memory withmemory locations identified by address values; wherein the methodcomprises the steps of:

[0027] a) assigning parts of the bus address space to different devicesconnected to the bus;

[0028] b) communicating a block of data to/from a bus master devicefrom/to a bus slave device in the form of a direct address transactionover the bus comprising one or more burst transactions consisting of anaddress phase followed by a data phase, the address phase including abus space address value;

[0029] c) storing in the memory of the indirect address device a blockof data communicated to the bus slave device , or retrieving from thememory of the indirect address device a block of data to be communicatedto the bus master device, in the form of an indirect addresstransaction, the indirect address transaction comprising an addressregister load transaction followed by a data register load transaction,the address register load transaction comprising a destination addressvalue for the received block of data;

[0030] wherein the method comprises the steps of:

[0031] d) prior to step c), translating the direct address transactionto the indirect address transaction including mapping the bus spaceaddress value to the destination address value.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] These and other features and advantages of the present inventionwill be better understood by reading the following detailed description,taken together with the drawings wherein:

[0033]FIG. 1 shows schematically a system bus for a computer to which anumber of devices are connected;

[0034]FIG. 2 shows schematically a burst transaction on a direct addressbus with address/data multiplexing;

[0035]FIG. 3 shows schematically multiple burst transactions on a directaddress bus with address/data multiplexing;

[0036]FIG. 4 shows schematically an indirect address transaction for anindirect address device;

[0037]FIG. 5 shows schematically how an address register of an indirectaddress device can be corrupted if a direct address device interruptstwo sequential direct address transactions to the indirect addressdevice;

[0038]FIG. 6 shows schematically how, according to a preferredembodiment of the invention, a single direct address transaction can betranslated to an indirect address transaction;

[0039]FIG. 7 shows a block circuit diagram of direct slave addressinterface logic used to translate a direct address transaction to anindirect address transaction; and

[0040]FIG. 8 shows schematically the translation by the circuit in FIG.7 of a single direct address transaction to an indirect addresstransaction.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041]FIG. 1 shows a block schematic diagram of a conventional computersystem 1, for example for a personal computer, having a system bus 2 towhich a number of devices 3-6 are connected. The system bus 2 is a32-bit PCIbus using address/data multiplexing with a direct addressprotocol for transferring data over the bus between devices 3-6.

[0042] The devices include a system central processor unit (μP) 3, arandom access memory (RAM) 4, a sound card (S) 5, and a graphics card(G) 6. For clarity, not shown are the usual other inputs to and outputsfrom each of the devices 3-6, such as a keyboard connection to themicroprocessor, a speaker output from the sound card 5, or a videomonitor output from the graphics card 6.

[0043] A bus arbiter device (A) 8 is also connected to the system bus 2.In additional to 32 address/data lines, the bus 2 includes a variety ofcontrol lines. One purpose of these control lines is to control accessto the bus 2. There may be only one bus master device at any one time,and the bus arbiter 8 controls which one of the devices 3-6 has accessto the bus 2 as a master device so that it may communicate with one ofthe other devices 3-6 as a slave device.

[0044] Either the microprocessor 3 or the sound card may be a masterdevice, while the random access memory 4 and graphics card 6 may only beslave devices.

[0045] As shown in FIG. 2, all the devices 3-6 communicate with eachother in a direct address protocol 10 in which one or more bursttransactions 11, as shown in FIG. 2, are communicated over the bus froma master device 3,5 to a slave device 3-6. The burst transactionconsists of an address phase 12 consisting of a 32-bit address wordfollowed by a data phase 13 consisting of one or more data words. Eachdevice 3-6 has assigned to it an address space on the system bus 2 . Theaddress word 12 therefore points to one of the devices as a slavedevice, and is interpreted by the slave device to be an address locationassociated with that device 3-6. The slave device receives the bursttransaction 10 with each data word 13 being stored in a location inmemory that is automatically incremented starting at the address value12.

[0046]FIG. 3 shows another example of the direct address protocol 20.The burst transaction 12 is interrupted and the master device 3,5, mustrequest use of the bus again. Once it is allowed access to the systembus 2 by the bus arbiter 8, it communicates a further burst transaction21 with an address value 22 incremented by an appropriate amount so thatthe remainder 23 of the data is transferred as a block to the correctaddress range associated with the slave device 3-6. The bursttransaction(s) 20 make up a direct address transaction.

[0047] Indirect addressing uses an indirect address protocol 30,comprising two sequential transactions, as shown in FIG. 4. The first ofthese transactions is an address register load transaction 31, which isfollowed by a data register load transaction 32.

[0048] As will be explained in greater detail below with reference toFIG. 7, the present example concerns the indirect addressing mechanismas used on a Texas Instruments (trade mark) TMS320C6 family of digitalsignal processors (DSP) 85 and its Expansion Bus (Xbus) 86. The indirectaddress transaction 30, involves firstly loading an address into theaddress register in the Xbus 86 before loading, or retrieving, a burstof one or more data words to, or from, the data register in the Xbus 86.This involves two separate accesses as shown in FIG. 4, where:

[0049] A_(A) is the address 33 of the address register.

[0050] A is the destination address 34 for the data in a DSP memory 77.

[0051] A_(D) is the address 35 of the data register.

[0052] D0, D1, D2, etc are the data words 36 to be loaded into addressesA, A+1, A+2, etc.

[0053] Note that in a burst access to the data register, the addressregister auto-increments so that it always contains the address of thenext data word in the data burst. Note also that these addresses12,22,34 are word addresses. If the bus is 32-bit, as is the case withthe Xbus 86 then the byte address equals the word address times four.

[0054] The advantage of the indirect addressing mechanism is that it cangive access to a large address area via just two registers. If we takefor example the PCIbus 2 connected to a TMS320C6 Xbus 86, the TMS320C6Xbus 86 has a local address space of 4 GB, all of which can be accessedvia two Xbus registers which can occupy just two PCIbus addresslocations.

[0055] Referring again to FIGS. 1-3, In a system such as PCIbus 2 whichallows multiple bus master devices 3,5 the various bus masters requestuse of the bus 2 when they have data to transfer across the bus 2 to thetarget device 3-6. The bus arbiter 8 is then responsible for grantingaccess to the bus 2. Once granted access to the bus 2, the bus master3,5 presents the address cycle 12 followed by one or more data cycles13. If this is a burst access then the data cycles 13 will continueuntil:

[0056] a) the bus master 3,5 completes its transfer.

[0057] b) the target device 3-6 tells the bus master 3,5 to terminatethe burst.

[0058] c) the bus master 3,5 terminates the burst if for instance itsFIFO buffers become full (read) or empty (write).

[0059] d) another bus master 3,5 has requested use of the bus and thebus arbiter 8 tells the current bus master 3,5 to relinquish control ofthe bus 2.

[0060] If the burst terminated before the bus master device 3,5 hascompleted its data transfer (i.e. cases b, c and d above) it mustre-arbitrate for use of the bus in order for it to complete itstransfer.

[0061] If multiple bus masters 3,5 are accessing a device 85 usingindirect addressing then there is a danger that in between the time thatthe bus master 3,5 writes to the address register and the data register,another bus master 3,5 may have written another value to the addressregister. This possibility 40 is illustrated in FIG. 5, where:

[0062] A_(A1) is the address 43 of the address register driven by afirst bus master.

[0063] A₁ is a first destination address 44, loaded by the first busmaster.

[0064] A_(A2) is the address 53 of the address register driven by asecond bus master.

[0065] A₂ is a second destination address 54 loaded by the second busmaster, thus corrupting the first value 44, previously loaded by thefirst bus master.

[0066] A_(D1) is an address 45 of the data register loaded by the firstbus master.

[0067] D0 ₁ is the first data word 46 loaded by the first bus master,intended to be loaded into the first destination address A₁ 44, whichwill in fact get loaded into the second destination address A₂ 54.

[0068] Note that the ‘corruption’ of the address register by second busmaster could occur between the first bus master's address register loadtransaction 41 and data register load transaction 42 (as shown in FIG.5), or it could occur when a burst transfer 42 to the data register getsbroken up into a series of bursts due to reasons b), c) or d) above.

[0069] Possible solutions for the problem of multiple bus master devicesare either to allow only a single bus master device 3,5 to access theindirect address device 85, or to disable all other bus master devices3,5 until an active bus master device has completed all phases of itstransfer. Both of these possibilities adversely affect the system'sflexibility, add additional complexity in controlling the multiple busmaster devices 3,5 and reduce the effective data transfer rate.

[0070] As mentioned above, bus master devices 3 driven by amicroprocessor can be programmed to carry out the two stage processinvolved in accessing a device, which uses indirect addressing. Othernon-intelligent bus master devices, such as the sound card 5, may onlyhave the ability to read or write blocks of data 13,23 to apre-programmed address. These devices 5 cannot be programmed to pre-loadthe address register of an indirect address device 85 prior to readingor writing its block of data. As a result such non-intelligent busmaster devices 5 cannot directly read and write data to a device 85,which uses indirect addressing.

[0071] An example of a non-intelligent bus master device is the widelyused Intel (trade mark) 82557 Ethernet LAN Controller. This is a PCIbusdevice for interfacing to 10BASE-T and 100BASE-T Ethernet. BufferDescriptors give the device the PCIbus address to which it should writeits receive data and from which it should read its transmit data. Withthe Xbus on the TMS320C6 family of DSPs using an indirect addressingmechanism this means that the Intel 82557 cannot read or write its databuffers directly from the TMS320C6 DSPs.

[0072] In the above example, to get data from the Intel 82557 to theTMS320C6 DSP, the data to/from the Intel 82557 must go via a buffermemory on the PCIbus where a microprocessor could then send, orretrieve, the data to, or from, the TMS320C6 DSP. This means that thedata must be sent twice over the PCIbus, thus consuming additional busbandwidth and adding latency to the transfer.

[0073] As described below with reference to FIGS. 6, 7 and 8, apreferred embodiment of the invention therefore provides “direct slaveaddress interface logic” 84,87 that allows bus master devices 3,5 on theaddress/data multiplexed direct address bus 2, for example the PCIbus,to directly address memory locations on a slave device 85 which alsouses an address/data multiplexed bus but which uses an indirectaddressing mechanism, for example the Expansion Bus Xbus 86 on the TexasInstruments TMS320C62 family of DSPs. The net result of this interfacelogic 84,87 is that any bus master 3,5 can read and write to the memory77 on the slave device 85 as if the memory 77 were directlymemory-mapped onto the bus 2.

[0074] The essence of the invention is summarised in FIG. 6. Theinterface logic 84,87 takes a direct address bus transaction 60,consisting of one or more burst transactions 61, each of which has anaddress phase 62 followed by a data phase, consisting of one or moredata cycles 63, and presents it to the indirect address device 85 as aslave bus transaction 70 consisting of two transactions 71,72. The first71 of these two transactions takes the address cycle 62 of the originaltransaction 61, and remaps 64 the address 62 to a remapped address value74 and writes this into the address register of the slave device 85. Ingeneral this remapping 64 will change the original address value 74, butthe remapping may in some cases leave the address value 74 unchanged.For a data write transaction it then takes the one or more data cycles63 and transfers 65 these to data values 76 of the data register loadtransaction 72 so that these are written without change into the dataregister of the slave device 85. This is shown in FIG. 6, where:

[0075] A_(B) is the address 62 of the slave device's memory 77 in themain bus's (e.g. the PCIbus 2) address space.

[0076] A_(S) is the remapped address value 74 generated from AB but isremapped 64 by the interface logic 84,87 to give the correct address inthe slave device's address space, and is then loaded into the addressregister of the slave device's Xbus 86.

[0077] A_(A) is the address 73 of the address register generated locallyby the interface logic 84,87.

[0078] A_(D) is the address 75 of the data register generated locally bythe interface logic 84,87.

[0079] D0, D1, D2 etc are the data words 76 to be loaded into addressesA_(S), A_(S)+1, A_(S)+2, etc of the slave device's memory 77.

[0080] The direct slave address interface logic 84,87 shown in FIG. 7has been implemented as part of a slave device 80 connected to the bus2, to interface between a 32-bit 33 MHz PCIbus 2 and the Expansion Bus(Xbus) 86 of a Texas Instruments TMS320C6202 DSP 85. The interface logicconsists of a PLX PCI-9054 PCIbus interface IC 87 and a Xilinx XC95288XLprogrammable logic IC 84, and supports the connection of fourTMS320C6202 DSPs 85 onto the PCI bus 2. Each of the DSPs 85 can be aPCIbus master or a PCIbus slave. The direct slave address interfacelogic 84,87 is also used to support local Xbus-to-Xbus data transfers,which would otherwise get corrupted, as described later. The variouscontrol lines of the Xbus 86 indicated in FIG. 7 are:

[0081] LAD—J-bus Address/Data Bus 83

[0082] XAD—Xbus Address/Data bits remapped by Programmable Logic 81

[0083] LCTRL—J-bus Control Signals 82 (LHOLD, LHOLDA, LADS, LW/R,LBLAST, LREADY, LWAIT, LBE[3:0])

[0084] XCTRL—Xbus Control Signals 88 (XHOLD, XHOLDA, XCS, XCNTL, XADS,XW/R, XBLAST, XREADY, XWAIT, XBOFF)

[0085]FIG. 7 will now be described in more detail, with reference alsoto FIG. 8. The PLX PCI-9054 chip 87 interfaces the PCIbus 2 through ontothe J-Bus address/data bus 83, remapping 64 a the PCIbus address (A_(B))62 to a required J-bus address (A_(J)) 94. The interface logic includesthe programmable logic array 84 that remaps 64 b the J-bus address(A_(J)) 94 to the required TMS320C6202 DSP memory address (A_(s)) 74.

[0086] Note that by careful design of the J-bus memory map it ispossible to minimise the number of J-bus Address/Data lines, which needto be remapped. Thus only those Address/Data lines which must beremapped need to connect via the programmable logic 84.

[0087] The programmable logic 84 also connects to all of the Xbuscontrol signals 88. “State machines” in the programmable logic 84generate 91 the Xbus 86 address register address cycle (A_(A)) 73, andalso generate 89 the Xbus 86 data register address cycle (A_(D)) 75.During the data cycles (D0, D1, D2 etc) 76 the J-bus Address/Datasignals 96 are passed 65 a,65 b transparently through the programmablelogic 84.

[0088] As shown in FIG. 8, this permits the translation of a singledirect address transaction 60 to be translated into an indirect addresstransaction 70 via a J-bus transaction 100 consisting of the J-busaddress (A_(J)) 94, followed by a short time delay 90 until theprogrammable logic has generated 89 the data register address cycle(A_(D)) 75. To summarise, FIG. 8 shows this for the case of a PCIbus 2to Xbus 86 direct slave address translation, where:

[0089] A_(B) is the address 62 of the DSP's memory 77 in PCIbus addressspace.

[0090] A_(J) is a J-bus address 94 taken from A_(B) 62 but remapped 64 aby the PLX PCI-9054 chip 87 to give the address 94 of the DSP's memory77 in J-bus address space.

[0091] A_(S) is the required DSP memory address 74 taken from A_(J) 94but remapped 64 b by the programmable logic 84 to give the address 74 ofthe DSPs' memory 77 in DSP address space, and is loaded into the Xbus 86address register.

[0092] A_(A) is the address 73 of the address register generated 91locally by the programmable logic 84.

[0093] A_(D) is the address 75 of the data register generated 89 locallyby the programmable logic 84.

[0094] D0, D1, D2 etc are the data words 76 to be loaded into DSPaddresses A_(S), A_(S)+1, A_(S)+2, etc.

[0095] A second preferred embodiment of the invention is shown in FIGS.9 and 10. For convenience, those parts of the drawings correspondingwith FIGS. 6 and 7 are indicated by reference numerals incremented by100. The second preferred embodiment provides “direct slave addressinterface logic” 184 that allows one TMS320C6 Xbus 185 as bus master todirectly address memory locations on a slave TMS320C6 Xbus device 185,which is connected to the same J-Bus 183. The net result of thisinterface logic 184 is that any Xbus as J-Bus master 185 can read andwrite to the memory 177 of the Xbus slave device 185 as if the memory177 were memory-mapped directly onto the bus 183. More importantly, the“direct slave address interface logic”, when used in conjunction withXbus “back-off” logic, allows master Xbus to slave Xbus read or writedata transfer across the J-Bus 183 without data corruption.

[0096] The direct slave address interface logic 184 shown in FIG. 9 hasbeen implemented to interface between the Xbuses 186 of four TexasInstruments TMS320C6202 DSPs 185. In this implementation, any one of thefour Xbuses is capable of mastering the J-Bus 183 and reading or writingto the memory of any of the other three indirect address slave Xbusdevices on the J-Bus 183 via the transaction translation deviceinterface logic. The various control lines of the Xbus 186 indicated inFIG. 9 are:

[0097] LAD—J-Bus Address/Data Bus 183

[0098] XAD—Xbus Address/Data bits remapped by programmable logic 181

[0099] XCTRL—Xbus Control Signals 188 (XHOLD, XHOLDA, XCS, XCNTL, XADS,XW/R, XBLAST, XREADY, XWAIT, XBOFF)

[0100]FIG. 9 will now be described in more detail, with reference alsoto FIG. 10. The interface logic consists of the programmable logic array184 that remaps 164 b the J-Bus address (A_(J)) 194 generated by themaster Xbus to the required slave TMS320C6202 DSP memory address (A_(S))174.

[0101] The programmable logic 184 also connects to all of the Xbuscontrol signals 188. “State machines” in the programmable logic 184generate 191 the slave Xbus 186 address register address cycle (A_(A))173, and also generates 189 the slave Xbus 186 data register addresscycle (A_(D)) 175. During the data cycles (D0, D1, D2 etc) 176 the J-BusAddress/Data signals 196 are passed 165 b transparently through theprogrammable logic 184.

[0102] As shown in FIG. 10, this permits the translation of a singledirect address transaction 200 to be translated into an indirect addresstransaction 170. To summarise, FIG. 10 shows this for the case of aXbus-to-Xbus 186 direct slave address translation, where:

[0103] A_(J) is the address 194 of the slave DSP's memory 177 in J-Busaddress space.

[0104] A_(S) is the required slave DSP memory address 174 taken fromA_(J) 194 but remapped 164 b by the programmable logic 184 to give theaddress 174 of the slave DSP's memory 177 in DSP address space, and isloaded into the slave Xbus 186 address register.

[0105] A_(A) is the address 173 of the slave Xbus address registergenerated 191 locally by the programmable logic 184.

[0106] A_(D) is the address 175 of the slave Xbus data registergenerated 189 locally by the programmable logic 184.

[0107] D0, D1, D2 etc are the data words 176 to be loaded into DSPaddresses A_(S), A_(S)+1, A_(S)+2, etc.

[0108] To avoid data corruption during master Xbus to slave Xbus datatransfers via the J-Bus, the burst transfer must be terminated byissuing a “Back off” to the master Xbus and a “Burst Last” to the slaveXbus, if during the transfer the slave Xbus is ready to send or receivethe next data word when the master Xbus is not ready. The logic issues a“Back off” by asserting XBOFF; it issues a “Burst Last” by assertingXBLAST; the slave Xbus is ready when it asserts XREADY and the masterXbus is not ready when it asserts XWAIT.

[0109] Adding the direct slave address interface logic 84,87;184 todevices 85,185 that operate with an indirect addressing interfaceenables the following:

[0110] 1) Multiple bus master devices 3,5,185 can perform unrestrictedconcurrent accesses to the indirect address slave device 85,185.

[0111] 2) Non-intelligent bus master devices 5 can read and write datadirectly to the slave device 85.

[0112] 3) When using Texas Instruments TMS320C62 family of DSPs whichare directly connected Xbus-to-Xbus, data can be transferred withoutcorruption so long as the “Back off” logic is also implemented.

[0113] The advantages provided by the invention in each of these threecases will now be considered in turn.

[0114] Unrestricted concurrent access to a slave device has a number ofperformance advantages. Firstly, data can be transferred directly fromsource to destination across the bus without the need for all data to govia a single system master device. This halves the bus bandwidth usedfor the transfer and more than halves the latency of the transfer.Secondly, all bus master devices can be permanently enabled without thedanger that one bus master device might corrupt the indirect addressregister setting of the indirect address device that has been set byanother bus master device. Without this, other bus master devices wouldhave to be disabled for the duration of every transfer to the Slave.This would result in inefficient bus usage, with data transfers beingdelayed. Finally, bus control is simplified since all bus master devicescan be left enabled.

[0115] Direct access to a slave device from a non-intelligent bus masterdevice provides the advantage that data can be transferred directly fromsource to destination across the bus without the need for all data to govia a single system master device. This halves the bus bandwidth usedfor the transfer and more than halves the latency of the transfer.

[0116] The TMS320C6 family of DSPs can transfer data directly to or fromother TMS320C6 DSPs, from Xbus-to-Xbus, without data corruption, so longas the Xbus-to-Xbus interface includes the “Transaction Translation”logic and the “Back-off” logic. Without the “Transaction Translation”logic and the “Back-off” logic, direct Xbus-to-Xbus data transferscannot be guaranteed to be free from data corruption. This has theadvantage that data can be transmitted directly from one TMS320C6 DSP toanother.

[0117] In conclusion, the direct slave address interface logic allowsbus masters on an address/data multiplexed bus (e.g. PCIbus or J-Bus) todirectly address memory locations on a slave device, which also uses anaddress/data multiplexed bus but which uses an indirect addressingmechanism, for example, the Expansion Bus (Xbus) on the TexasInstruments TMS320C62 family of DSPs.

[0118] The direct slave address interface logic thus allows multiple busmasters to perform unrestricted concurrent accesses using byte, word orburst data read or write transfers to a slave device that uses anindirect addressing mechanism. It also allows non-intelligent bus masterdevices to read and write data directly to an indirectly addressableslave device.

[0119] In particular the direct slave address interface logic allows theExpansion Bus on the Texas Instruments TMS320C62 family of DSPs toconnect to a PCIbus such that its memory is directly memory-mapped intothe PCIbus's address space.

[0120] The direct slave address interface logic also allows two TexasInstruments TMS320C62 family DSP devices to connect to each other viatheir Expansion Bus (XBus) ports such that they can transfer bursts ofdata between each other without data corruption.

[0121] The invention therefore provides a convenient and economicalsolution to the problems associated with integrating an indirect addressdevice with a direct address bus.

[0122] Modifications and substitutions by one of ordinary skill in theart are considered to be within the scope of the present invention whichis not to be limited except by the claims which follow.

What is claimed is:
 1. A computer bus system, comprising: a bus; atleast one bus master device and at least one bus slave device, the busmaster device and bus slave device being connected to the bus so thatthe bus master device may communicate with the bus slave device over thebus; wherein: i) the bus has an address space with parts of the busaddress space being assigned to different devices connected to the bus;ii) the bus is a multiplexed address/data bus for transferring in adirect address transaction between said devices, blocks of data, each ofsaid direct address transactions comprising one or more bursttransactions consisting of an address phase followed by a data phase,the address phase including a bus space address value; iii) the busslave device includes an indirect address device, addressable in anindirect address transaction, said transaction comprising an addressregister load transaction followed by a data register load transaction;iv) the indirect address device has a memory with memory locationsidentified by address values; v) the address register load transactioncomprises a destination address value for blocks of data communicatedto/from the memory of the indirect address device; wherein the slavedevice includes a transaction translation device between the bus and theindirect address device, the transaction translation device beingadapted to translate a direct address transaction on the bus to anindirect address transaction including a mapping of the bus spaceaddress value to the destination address value.
 2. The computer bussystem of claim 1, in which: i) the address values for the indirectaddress device may be used to identify both an address register and adata register in the indirect address device; ii) the address registerload transaction for blocks of data communicated to/from the memory ofthe indirect address device comprises two address values: an addressregister address value and the destination address value; iii) the dataregister load transaction includes a data register address value; andwherein the transaction translation device, as part of the translationof the direct address transaction to the indirect address transaction,generates both the address register address value and the data registeraddress value.
 3. The computer bus system of claim 1, in which a blockof data comprises one or more data words, the data register loadtransaction comprising the data register address value followed by oneor more of the data words.
 4. The computer bus system of claim 1,wherein the address of the address register and the address of the dataregister are both fixed and generated internally by the transactiontranslation device.
 5. The computer bus system of claim 1, in which theaddress register address value and/or the data register address valueis/are alterable and stored in the transaction translation device.
 6. Amethod of communicating blocks of data over a computer bus system, thesystem comprising: a bus, the bus having an address space and being amultiplexed address/data bus for transferring in a direct addresstransaction blocks of data; at least one bus master device and at leastone bus slave device, the bus master device and bus slave device beingconnected to the bus so that the bus master device may communicate withthe bus slave device over the bus, the bus slave device including anindirect address device; the indirect address device has a memory withmemory locations identified by address values; wherein the methodcomprises the steps of: a) assigning parts of the bus address space todifferent devices connected to the bus; b) communicating a block of datato/from a bus master device from/to a bus slave device in the form of adirect address transaction over the bus comprising one or more bursttransactions consisting of an address phase followed by a data phase,the address phase including a bus space address value; c) storing in thememory of the indirect address device a block of data communicated tothe bus slave device, or retrieving from the memory of the indirectaddress device a block of data to be communicated to the bus masterdevice, in the form of an indirect address transaction, the indirectaddress transaction comprising an address register load transactionfollowed by a data register load transaction, the address register loadtransaction comprising a destination address value for the receivedblock of data; wherein the method comprises the steps of: d) prior tostep c), translating the direct address transaction to the indirectaddress transaction including mapping the bus space address value to thedestination address value.